Intel 30167003 P8
Dual-Channel Asymmetric
This mode is entered when both memory channels are routed and populated with different
amounts (MB) of total memory. This configuration allows addresses to be accessed in series
across the channels starting in channel A until the end of its highest rank, then continue from the
bottom of channel B to the top of the rank. Real world applications are unlikely to make requests
that alternate between addresses that sit on opposite channels with this memory organization, so
in most cases, bandwidth will be limited to that of a single channel.
Dual-Channel Symmetric
This mode allows the end user to achieve maximum performance on real applications by utilizing
the full 64-bit dual-channel memory interface in parallel across the channels with the aid of Intel®
Flex Memory Technology. The key advantage this technology brings is that the end user is only
required to populate both channels with the same amount (MB) of total memory to achieve this
mode. The DRAM component technology, device width, device ranks, and page size may vary
from one channel to another.
Addresses are ping-ponged between the channels, and the switch happens after each cache line
(64 byte boundary). If two consecutive cache lines are requested, both may be retrieved
simultaneously, since they are guaranteed to be on opposite channels.
内存Slot的显示问题,大概是因为这个,我也不是太懂:
Intel Document Number: 305264-001
Mobile Intel® 915 PM/GM/GMS and 910GML Express Chipset Datasheet P37
Data Bus:
DDR / DDR2 Channel A data signal interface to the SDRAM data
bus.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
发表于 2005-10-15 01:52
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发表于 2005-10-15 02:11
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